library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use work.dec_pkg.all;

entity denominator is
port(
      clk: in std_ulogic;
		q1,q2,q3,q4,q5,q6,q7,q8: in std_ulogic_vector(15 downto 0);
		--p1,p2,p3,p4,p5,p6,p7,p8: out std_ulogic_vector(15 downto 0);
		vtmp_w1,vtmp_w2,vtmp_w3,vtmp_w4,vtmp_w5,vtmp_w6,vtmp_w7,vtmp_w8: out std_ulogic_vector(15 downto 0)
		);
end denominator;

architecture beh of denominator is

signal  delt1,delt2,delt3,delt4,delt5,delt6,delt7,delt8:std_ulogic_vector(15 downto 0);
signal  dd_w1,dd_w2,dd_w3,dd_w4,dd_w5,dd_w6,dd_w7,dd_w8:std_ulogic_vector(18 downto 0);

begin


------------*************************?8?q??????????****************************
--process(clk)
--  begin
--    if clk'event and clk='1'  then
--        p1<=q1;
--        p2<=q2;
--        p3<=q3;
--        p4<=q4;
--        p5<=q5;
--        p6<=q6;
--        p7<=q7;
--		    p8<=q8;
--    end if;
--end process;


----------***********************??????q???????????****************************
process(clk)
  begin
   if clk'event and clk='1'  then
   delt1<=consult_pos(q1);
	 delt2<=consult_pos(q2);
	 delt3<=consult_pos(q3);
	 delt4<=consult_pos(q4);
	 delt5<=consult_pos(q5);
	 delt6<=consult_pos(q6);
	 delt7<=consult_pos(q7);
	 delt8<=consult_pos(q8);
   end if;
end process;

process(delt1,delt2,delt3,delt4,delt5,delt6,delt7,delt8)
  begin
   dd_w1<= ("000"&delt2)+("000"&delt3)+("000"&delt4)+("000"&delt5)+("000"&delt6)+("000"&delt7)+("000"&delt8); 
   dd_w2<= ("000"&delt1)+("000"&delt3)+("000"&delt4)+("000"&delt5)+("000"&delt6)+("000"&delt7)+("000"&delt8); 
   dd_w3<= ("000"&delt1)+("000"&delt2)+("000"&delt4)+("000"&delt5)+("000"&delt6)+("000"&delt7)+("000"&delt8); 
   dd_w4<= ("000"&delt1)+("000"&delt2)+("000"&delt3)+("000"&delt5)+("000"&delt6)+("000"&delt7)+("000"&delt8); 
   dd_w5<= ("000"&delt1)+("000"&delt2)+("000"&delt3)+("000"&delt4)+("000"&delt6)+("000"&delt7)+("000"&delt8); 
   dd_w6<= ("000"&delt1)+("000"&delt2)+("000"&delt3)+("000"&delt4)+("000"&delt5)+("000"&delt7)+("000"&delt8); 
   dd_w7<= ("000"&delt1)+("000"&delt2)+("000"&delt3)+("000"&delt4)+("000"&delt5)+("000"&delt6)+("000"&delt8); 
   dd_w8<= ("000"&delt1)+("000"&delt2)+("000"&delt3)+("000"&delt4)+("000"&delt5)+("000"&delt6)+("000"&delt7); 
  end process;

process(clk)
begin
  if clk'event and clk='1'  then
    if (dd_w1(17) or dd_w1(16) or dd_w1(15)or dd_w1(14))='1'  then
	     vtmp_w1<="0011111111111111";
    else
	     vtmp_w1<=dd_w1(15 downto 0);
	 end if;
	 
	 if (dd_w2(17) or dd_w2(16) or dd_w2(15)or dd_w2(14))='1'  then
	     vtmp_w2<="0011111111111111";
    else
	     vtmp_w2<=dd_w2(15 downto 0);
	 end if;
	 
	 if (dd_w3(17) or dd_w3(16) or dd_w3(15)or dd_w3(14))='1'  then
	     vtmp_w3<="0011111111111111";
    else
	     vtmp_w3<=dd_w3(15 downto 0);
	 end if;
	 
    if (dd_w4(17) or dd_w4(16) or dd_w4(15)or dd_w4(14))='1'  then
	     vtmp_w4<="0011111111111111";
    else
	     vtmp_w4<=dd_w4(15 downto 0);
	 end if;
	 
	 if (dd_w5(17) or dd_w5(16) or dd_w5(15)or dd_w5(14))='1'  then
	     vtmp_w5<="0011111111111111";
    else
	     vtmp_w5<=dd_w5(15 downto 0);
	 end if;
    
	 if (dd_w6(17) or dd_w6(16) or dd_w6(15)or dd_w6(14))='1'  then
	     vtmp_w6<="0011111111111111";
    else
	     vtmp_w6<=dd_w6(15 downto 0);
	 end if;
	 
	 if (dd_w7(17) or dd_w7(16) or dd_w7(15)or dd_w7(14))='1'  then
	     vtmp_w7<="0011111111111111";
    else
	     vtmp_w7<=dd_w7(15 downto 0);
	 end if;
	 
	 if (dd_w8(17) or dd_w8(16) or dd_w8(15)or dd_w8(14))='1'  then
	     vtmp_w8<="0011111111111111";
    else
	     vtmp_w8<=dd_w8(15 downto 0);
	 end if;
	end if;
end process;


end beh;

